Digital System Integration

Please note

This document only provides information for the academic year selected and does not form part of the student contract

School:

School of Computing and Engineering

Credit Rating:

Level (including FHEQ):

H (FHEQ Level 6)

Graded or Non Graded:

Graded

Version Valid From:

2022-09-01

Module Leader:

Faheem Khan

Version Number

2023.01

Learning Methods

Guided Independent Study

Tutorial and Project Supervision

Lecture

Practical Classes and Demonstrations

Requirements

Recommended Prior Study

Professional Body Requirements

Institution of Engineering and Technology

Synopsis

Digital System Integration is becoming increasingly important in modern electronics. In this module, you will be introduced to system design, circuit design, modelling, layout, and fabrication techniques for CMOS and Bipolar (minimal) integrated circuits. You will investigate various stages of design: from integration, transistor, and circuit to system; decomposition from … For more content click the Read More button below.

Digital System Integration is becoming increasingly important in modern electronics. In this module, you will be introduced to system design, circuit design, modelling, layout, and fabrication techniques for CMOS and Bipolar (minimal) integrated circuits. You will investigate various stages of design: from integration, transistor, and circuit to system; decomposition from Hardware Description Language (HDL) whilst emphasising the Register Transfer Level RTL/gate level decisions. You will also learn about the design trade-offs required to achieve an optimum design solution.

Learning Strategy

In this module the learners will engage in a blend of delivery methods facilitating both individual and collaborative aspects of learning to achieve the specified learning outcomes. In particular, this will require the learner to engage with the VLE materials where the learning is supported by the tutor-led two-way asynchronous discussion board. To focus the guided learning process, the tutor will set weekly quizzes/assignments (SAIL). These two elements will culminate in face-to-face sessions which will reinforce the learning by clarifying the content through student-led questions/answers interaction. These sessions are followed up by tutorials to illustrate the module content and enable practice in more depth. Lectures with integrated tutorial and seminar activity will be used to address all outcomes. Supervised laboratory sessions will be run to support Task 2. Unsupervised time will be used to prepare for and complete Task 2, tutorial work, guided reading, and revision. The module will make use of C&IT in the following ways: VHDL simulation package in design and assignment work. Internet access for research papers, data sheets, design notes, application data, this will supplement the module content and assignment work. Brightspace is used to support and supplement both the lecture and laboratory work. The module is supported by the use of BrightSpace VLE including course documentation, pre-recorded lectures, external links, communication/discussion and self-assessment facilities. Students with disability will be accommodated by close adherence to the University of Huddersfield guidelines which inter alia include: (i) pre-recorded materials with captions of suitable size, (ii) Power Point slides following the appropriate font size and colour contrast, (iii) early availability of all materials on VLE – typically at least two weeks in advance.

Outline Syllabus

SYSTEM LEVEL
Fundamental analysis of current digital system development, identifying cost drivers whilst also investigating future techniques.
System level approach to digital system specification.
System level modelling using an appropriate Hardware Description Language (HDL).
Design decomposition and circuit level system design implementation using macro structures and advanced Finite State Machine (FSM) design techniques.
Logic Synthesis techniques (FPGA development).
Error coding techniques.
Pipelining techniques.
Test, Design For Test (DFT) and fault modelling.
Asynchronous effects and interfacing in synchronous systems.
LAYOUT LEVEL
Field-Effect Transistors: NMOS, PMOS, MOS transistor fabrication and layout design, MOS biasing.
JFET: Depletion and Enhancement JFET, JFET biasing.
Logic gates: Logic level definition, noise margin, dynamic response. NMOS inverter design, NMOS NAND and NOR gates, power dissipation.
CMOS logic design: CMOS inverter: static and dynamic behaviour, power dissipation, CMOS NOR and NAND gates, Transmission gates, multiplexers, latches, and flip-flops.

Learning Outcomes

On successful completion of this module students will

Apply modern digital CAD tools and Hardware Description Languages (HDLs) to the development and analysis digital design problems.

Apply the underpinning principles, tools and notations proficiently in the design and analysis of digital circuit/system problems.

Evaluate the methodologies, techniques, performance limitation factors and cost drivers for the design of digital systems.

Demonstrate an awareness of developing technologies related to integrated circuit design.

Analyse data for a design problem (before solving) using an appropriate design methodology and assess the quality of the solution.

Formative Assessment

Assessment 1: Focused classwork observations

Assessment 2: Oral presentation/assessment

Assessment 3: Practical skills assessment

Summative Assessment

Assessment 1: Written Assignment

Description:Taught material will contribute an element every week to the SAIL programme (Score As I Learn) submitted via the VLE platform. 11 x 15 minutes weekly assignments. Each assignment will be worth 3%. Taking the best 8 out of 11 scores.

Assessment Weight:24

Assessment Length:10 Hours (Typical Effort)

Module Learning Outcomes:MLO2, MLO3, MLO4, MLO5

Individual or Group:Individual

Final Assessment Component:No

Marked Anonymously:Yes

Eligible for Tutor Reassessment:No

Assessment 2: Written Assignment

Assessment 3: In-Class Test

Assessment Criteria

Task 1
SAIL
Task 2
2.1 Well-developed skills in the interpretation of questions and the selection of appropriate techniques and models for their solution are evident.
2.2 Models and techniques are applied accurately with partial solutions and solutions checked for consistency as work progresses.
2.3 Written explanations are complete, unambiguous and make appropriate use of diagrams, tables, and graphs etc.
2.4 Explain the operation of a digital system, showing a clear understanding of the operation of the system and the supporting analysis.
2.5 Correct application of analytical and mathematical methods in analysing digital systems/circuits and solving problems.
2.6 Logical discussion based on relevant parameters comparing the performance of digital systems and selecting the most suitable for a given application.
Task 3
3.1 Demonstrate an ability to extract and critically evaluate data for an unfamiliar problem.
3.2 Correct application of appropriate design methods to a digital system.
3.3 Select appropriate modelling and analysis tools for system design and simulation.
3.4 Ability to implement a design solution on a commercially available digital Computer Aided Design (CAD) tool.
3.5 Critically evaluate and test the developed solution, reporting results in the form of a formal report in the recommended format.

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